1. Field of the Disclosure
The present disclosure generally relates to synchronous circuits and, more particularly, to a system and method to centralize the lock point of a synchronous circuit.
2. Brief Description of Related Art
Most digital logic implemented on integrated circuits is clocked synchronous sequential logic. In electronic devices such as synchronous dynamic random access memory circuits (SDRAMs), microprocessors, digital signal processors, etc., the processing, storage, and retrieval of information is coordinated or synchronized with a clock signal. The speed and stability of the clock signal determines to a large extent the data rate at which a circuit can function. Many high speed integrated circuit devices, such as SDRAMs, microprocessors, etc., rely upon clock signals to control the flow of commands, data, addresses, etc., into, through and out of the devices.
In SDRAMs or other memory devices, it is desirable to have the data output from the memory synchronized with the system clock that also serves the microprocessor. Delay-locked loops (DLLs) are synchronous circuits used in SDRAMs to synchronize an external clock (e.g., the system clock serving a microprocessor) and an internal clock (e.g., the clock used internally within the SDRAM to perform data read/write operations on various memory cells) with each other. Typically, a DLL is a feedback circuit that operates to feed back a phase difference-related signal to control a delay line, until the timing of one clock signal (e.g., the system clock) is advanced or delayed until its rising edge is coincident (or “locked”) with the rising edge of a second clock signal (e.g., the memory internal clock).
FIG. 1 depicts a simplified block diagram of a prior art delay-locked loop (DLL) 10 that can be internal to an SDRAM (not shown). The DLL 10 receives a reference clock 12 as an input and generates an output clock or the CLKOut signal 13 at its output. A Tree_CLK signal 13* is, in turn, fed back as a feedback clock 14 as discussed later. The reference clock 12 is interchangeably referred to herein as “Ref” or “Ref clock signal” or “Ref clock”; whereas the feedback clock 14 is interchangeably referred to herein as “FB” or “FB clock signal” or “FB clock.” The reference clock 12 is typically the external system clock serving the microprocessor or a delayed/buffered version of it. In the embodiment of FIG. 1, the system clock CLK 24 and its inverted version CLK_25 are fed into a clock receiver 23 and appear at the receiver's outputs 26 and 27, respectively. The system clocks are then buffered through a clock buffer 28. One output of the clock buffer 28—i.e., the Ref clock 12—thus is a buffered version of the system clock CLK 24. The other output 30 of the clock buffer 28 is a buffered version of the inverted system clock CLK_25 or the inverted version of the Ref clock 12. This output 30 of the clock buffer 28 is interchangeably referred to herein as the “inverted reference clock” or “Ref* clock” or “Ref* clock signal.” In traditional synchronous circuits with a single delay line (e.g., the DLL circuit 10 with a delay line 16), only the Ref clock 12 is input into the delay line as shown in FIG. 1.
The Ref clock 12 may be fed into the delay line 16 via a buffer 15. The output of the buffer 15 is a CLKIn signal 17, which is a buffered version of the reference clock 12. The clock output of the delay line 16—the CLKOut signal 13—is used to provide the internal clock (not shown) used by the SDRAM to perform data read/write operations on memory cells and to transfer the data out of the SDRAM to the data requesting device (e.g., a microprocessor). Thus, as shown in FIG. 1, the CLKOut 13 is sent to a clock distribution network or clock tree circuit 20 whose output 21 may be coupled to SDRAM clock driver and data output stages to clock the data retrieval and transfer operations. As can be seen from FIG. 1, the CLKOut signal 13 (and, hence, the FB clock 14) is generated using a delay line 16, which introduces a specific delay into the input Ref clock 12 (or CLKIn 17) to obtain the “lock” condition.
A phase detector (PD) 18 compares the relative timing of the edges of the system clock CLK 24 and the memory's internal clock (not shown) by comparing the relative timing of their respective representative signals—the input clock signal (the Ref clock 12) which relates to the system clock 24, and the FB clock signal 14 which relates to the memory's internal clock—so as to establish the lock condition. As shown in FIG. 1, an I/O model circuit 22 may be a part of the DLL 10 to function as a buffer or dummy delay circuit for the Tree_CLK signal 13* before the Tree_CLK signal 13* is fed into the phase detector 18 as the FB clock 14. The Tree_CLK signal 13* may be obtained from the clock tree circuit 20 in such a manner as to make the FB clock 14 effectively represent the memory's internal clock, which may be present through the clock driver and data output stages. The I/O model 22 may be a replica of the system clock receiver 23, the external clock buffer 28, and the clock and data output path (including the clock driver coupled to the output 21) so as to match respective delays imparted by these stages to the system clock 24 and the CLKOut signal 13, thereby making the Ref clock 12 and the FB clock 14 resemble, respectively, the system clock CLK 24 and the internal clock of the memory as closely as possible. Thus, the I/O model 22 attempts to maintain the phase relationship between the Ref clock 12 and the FB clock 14 as close as possible to the phase relationship that exists between the system clock CLK 24 and the memory's internal clock. The Ref clock 12 and the FB clock 14 are fed as inputs into the phase detector 18 for phase comparison. The output of the PD 18—a delay adjustment signal or indication 19—controls the amount of delay imparted to the CLKIn signal 17 by the delay line 16.
The delay adjustment signal 19 may determine whether the Ref clock 12 should be shifted left (SL) or shifted right (SR) through the appropriate delay in the delay line 16 so as to match the phases of the Ref clock 12 and the FB clock 14 to establish the lock condition. The delay imparted to the Ref clock 12 by the delay line 16 operates to adjust the time difference between the output clock (i.e., the FB clock 14) and the input Ref clock 12 until they are aligned. The phase detector 18 generates the shift left and shift right signals depending on the detected phase difference or timing difference between the Ref clock 12 and the FB clock 14.
FIG. 2 illustrates exemplary timing relationships among various clock signals operated on by the phase detector 18 in the DLL 10 in FIG. 1. The Ref clock 12 and the FB clock 14 are input to the phase detector 18, which generates the shift left or shift right signals depending on whether the rising edge of the Ref clock 12 appears before or after the rising edge of the FB clock 14. In practice, the DLL 10 is considered “locked” (i.e., the Ref clock 12 and the FB clock 14 are “synchronized”) when the rising edges of the Ref clock 12 and the FB clock 14 are substantially aligned. As shown in part (a) in FIG. 2, when the Ref clock 12 is “leading” or “faster” than the FB clock 14 (i.e., when the rising edge of the Ref clock 12 appears before the rising edge of the FB clock 14) by a time amount equal to “tPE”, the PD 18 may generate a shift right (SR) indication to instruct the delay line 16 to right shift the Ref clock 12 by “tPE” to achieve the lock condition. Similarly, as shown in part (b) in FIG. 2, when the Ref clock 12 is “slower” than or “lagging” the FB clock 14 (i.e., when the rising edge of the Ref clock 12 appears after the rising edge of the FB clock 14) by the time amount “tPE”, the PD 18 may generate a shift left (SL) signal to instruct the delay line 16 to left shift the Ref clock 12 by “tPE” to establish the lock. The parameter “tPE” (tPE>0) may indicate a small phase error between the FB clock 14 and the Ref clock 12, especially when the FB clock 14 is almost in phase with the Ref clock 12. As discussed below with reference to FIG. 3, in such a situation, the DLL 10 may lock to the either end of the delay line 16.
FIG. 3 depicts delay line lock point locations for the clock signals in FIG. 2 using a traditional DLL locking mechanism (e.g., the DLL 10 in FIG. 1). In conventional DLL locking mechanisms, when the feedback signal (the FB clock 14) is almost in phase with the reference signal (the Ref clock 12), as illustrated in parts (a) and (b) in FIG. 2, the DLL may lock to either end of the delay line 16. FIG. 3 symbolically designates the right end of the delay line 16 as its initial signal entry point 31. In case (b) in FIG. 2, upon entry into the delay line 16 at the initial entry point 31, the Ref clock 12 may be shifted left to establish the lock point 33 that represents a delay of “tPE” from the initial entry point 31. Thus, the lock point 33 remains close to the right end of the delay line 16. On the other end, for case (a) in FIG. 2, because the initial entry point 31 is fixed at the right end of the delay line 16, the Ref clock 12 may not be further shifted right by “tPE”, but, instead, may have to be shifted left by an amount of delay equal to “tCK−tPE” so as to establish the lock point 32 close to the other (left) end of the delay line 16. The clock period of the Ref clock 12 (or the Ref* 30) is designated as “tCK.” As is observed with reference to the traditional lock point establishment mechanism illustrated in FIG. 3, there may not be enough room for additional tuning or locking range after the initial lock is established or a longer lock time may be required because of the locking performed towards either end of the delay line 16, instead of towards the center of the delay line. For example, in case of the lock point (b) in FIG. 3, an additional spare delay 34 may be required as part of the delay line 16 for better tuning range (e.g., to accommodate voltage, temperature and frequency fluctuations) after the initial lock 33. The spare delay 34 may increase circuit power consumption and may represent additional hardware. On the other hand, in case of the lock point (a) in FIG. 3, a force-shift-left logic may be required to left shift the Ref clock 12 from the initial entry point 31. Also, in case of lock point (a), longer lock time (from “tPE” to “tCK−tPE”) and, hence, longer delay line 16 may be required.
Therefore, it is desirable to lock a digital synchronous circuit (e.g., a DLL) at the center of or close to the center of the delay line to reduce initial lock time and provide extra tuning range in the event of voltage, temperature and frequency changes after the initial lock is established, but without increasing the size or changing the configuration of the delay line or without requiring a spare delay. When the synchronous circuit is tuned at the center or close to the center of its delay line, more room is available to accommodate voltage, temperature and frequency fluctuations that may affect the initially-established lock.